TS-7800 User's Manual
(preliminary version 0801151006)
Introduction
The
TS-7800 is a PC-104 form factor, high performance single board computer
(SBC) designed for running Linux "out of the box". Its hardware
features include:
- 500 MHz ARM9 CPU (3x faster then previous TS-72XX boards)
- Internal PCI bus
- PC/104 connector
- 128MB DDR-RAM
- 512MB NAND Flash (17MB/s)
- 12,000 LUT user-programmable FPGA
- Gigabit Ethernet, 10/100/1000 speeds
- dual SATA ports, dual SD sockets
- dual USB2.0 High-Speed Host/Slave
- Sleep mode uses 200 microamps
Software features include:
- Unbrickable design
- Backward-compatible with TS-72xx boards
- Boots Linux in < 2 seconds
- Linux 2.6 and Debian
The
TS-7800 utilizes a Marvell 88F5182 ("Media Vault") CPU which implements
the SATA2, Gigabit Ethernet, USB 2.0, and COM1/COM2
functionality. For technical information on these functions
please refer to the datasheets available from Marvell. (Currently
a preliminary datasheet
is available.) The TS-7800 also utilizes a Lattice ECP2 (LFE2-12E)
FPGA; please refer to datasheets available from Lattice for more
information.
Getting Started
The TS-7800 provides three
separate boot mechanism: on-board flash, SD, and micro SD. To
boot from the on-board flash, remove JP1. To boot from micro SD,
install JP1 and a bootable micro SD card. To boot from SD,
install JP1, ensure that no micro SD card is present, and insert a
bootable SD card.
All boot methods as shipped from the factory
default to a fastboot, which provides a busybox prompt in under two
seconds. When this shell is exited the board continues on to
perform a full Debian boot.
SD card features
The SD
cards shipped with and for the TS-7800 contain a special four partition
scheme. The first partition is a VFAT partition. On cards
larger then 1GB, this partition contains Eclipse and other tools,
documentation, and so forth. On cards smaller then 1GB this
partition is empty. The second partition contains a raw image of
the kernel to be booted on the board, while the third partition
contains an initial ramdisk (initrd) which the kernel uses as its root
filesystem until the fastboot shell exits. The fourth partition
contains the Debian Linux distribution, and contains the root
filesystem that is used when the fastboot shell exits and the full boot
commences.
Board specific features
Jumpers
JP1 (boot select)
Sampled
at power-up. When ON, the board will first try to boot from the
micro-SD card, and then from the SD card, and finally if both of those
fail it will attempt to boot from the on-board flash. When
OFF, only the last step (boot from on-board flash) is attempted.
Software
can sample the value of this jumper by reading bit 30 at address
0xE8000004. If this bit is set, JP1 is ON, otherwise it is OFF.
JP2
Sampled
at power-up. When OFF, the bootrom will not send any messages to
the console port (COM1). When ON, the opposite is
true. Note that it is up to the operating system kernel loaded as
to whether or not it will send messages to the console port. For
instance, in Linux the CONFIG_CMDLINE kernel parameter and verbosity
level control where boot-up messages go.
Software can sample the
value of this jumper by reading bit 31 at address 0xE8000004. If
this bit is set, JP2 is ON, otherwise it is OFF.
JP3
Sampled at power-up. When OFF, the CPU will run at 500MHz. When ON, the CPU will run at 400MHz.
LEDs
There are two LEDs on the TS-7800: one RED and one GREEN.
The GREEN LED blinks once at power-up to indicate that the power-up
sequence succeeded.
Both LEDs can be turned on or off under
software control. The GREEN LED is accessed via bit 30 at address
0xE8000008. A value of 1 corresponds to the LED being on.
The RED LED is accessed indirectly through the on-board AVR
microcontroller. Please refer to the source code of the ts7800ctl program as a reference for controlling this LED.
Microsecond Counter
The
TS-7800 has a counter which is incremented every microsecond. This can
be used to increase the precision of short time measurements, for
example. The 32-bit value at address 0xE8000040 contains the
counter.
Random Number Generator
The TS-7800 has a
built-in true random number generator (RNG). The
number is generated from internal random entropy. The 32-bit
value at address 0xE8000040 contains the most recent random value
generated. Only thirty-two bits of true random data are created every
second, so if this register is read more quickly the values read are
not guaranteed to be random: in fact, you will either read the same
value as previously or else a pseudo-random intermediate value from the
last value generated.
LCD header
The LCD header is a 14 pin
(2x7, 0.1" spacing) header with open-drain pull-ups. A low (0)
output value will sink current, while a high (1) output value will only
tri-state. This header is 5V tolerant. Open drain outputs
can sink 8mA, but can only source current through the pull-up resistor.
There
are two register bits for each pin on the LCD header: an output bit,
the value of which controls whether the pin is low (0) or tri-stated
(1), and an input bit, which contains the signal value present on the
pin.
The LCD header is numbered as follows:
(Pin 1 is next to the dot on the silkscreen)
Input
bits are read from address 0xE8000004 and output bit are written to
address 0xE8000008. The register bits are as follows:
pin
| bit
| pull
| LCD function |
1
| 16
| +5V
| Vcc
|
2
| 17
| GND
| GND
|
3
| 18
| N/A
| contrast (bias)
|
4
| 19
| 470ohm
inline
| RS
|
5
| 20
| 51.1ohm
(1%) inline
| RW
|
6
| 21
| N/A
| E
|
7
| 22
| HI via 2.2k
| DB0
|
8
| 23
| HI via 2.2k | DB1
|
9
| 24
| HI via 2.2k | DB2
|
10
| 25
| HI via 2.2k | DB3
|
11
| 26
| HI via 2.2k | DB4
|
12
| 27
| HI via 2.2k | DB5
|
13
| 28
| HI via 2.2k | DB6
|
14
| 29
| HI via 2.2k | DB7
|
Please note
that pin 1 of the LCD header is tied to +5V and pin 2 is tied to
ground; these pins are therefore not controllable through the output
bit.
DIO header
The DIO header operates in a very similar manner as the LCD header.
The DIO header is numbered as follows:
(Pin 1 is next to the dot on the silkscreen)
Input
bits are read from address 0xE8000004 and output bit are written to
address 0xE8000008. The register bits are as follows:
pin
| bit
| pull
| extra
|
1
| 0
| HI via 2.2k
|
|
2
| 1
| HI (*)
|
|
3
| 2
| HI via 2.2k |
|
4
| 3
| HI (*) |
|
5
| 4
| HI via 2.2k |
|
6
| 5
| HI (*) | SPI_FRAME
|
7
| 6
| HI via 2.2k |
|
8
| 7
| HI (*) |
|
9
| 8
| HI via 2.2k |
|
10
| 9
| HI via 4.7k
| SPI_MISO#
|
11
| 10
| HI via 2.2k |
|
12
| 11
| HI (*) | SPI_MOSI
|
13
| 12
| HI via 2.2k |
|
14
| 13
| HI (*) | SPI_CLK
|
15
| 14
| HI via 2.2k |
|
16
| 15
| HI (*) |
|
(*) pulled high internally through 20k-150k nominal resistance.
The
"extra" bits denote which pins have alternate meanings. However
the implementation of these pins is left up to user software.
Temperature Sensor (optional)
The
TS-7800 has an optional on-board temperature sensor (part
#:OP-TMPSENSE). The temperature sensor used is a TMP124; a
copy of the datasheet can be found here, and sample code can be found here.
PC-104 connector
The
PC-104 connector consists of pins in four rows labelled A, B, C, and D.
The numbering of the pins in each row is shown below:
|
| 19
| 18
| 17
| 16
| 15
| 14
| 13 | 12
| 11 | 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3 | 2 | 1
| 0
| 19
| 18
| 17
| 16
| 15
| 14
| 13
| 12
| 11 | 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
|
| 32
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 32
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
|
|
The
PC-104 connector can be multiplexed between different functionalities
including ISA bus and GPIO. The power-up default is GPIO
mode, with all I/Os in a neutral state. To enable the PC-104 bus
(ISA) signals, it is necessary to write the following values to the
registers specified:
0x55555555 to address 0xE8000030
0x55555555 to address 0xE8000034
0x55555 to address 0xE8000038
0x55555 to address 0xE800003C
More
specifically, the functionality of the PC-104 connector can be
configured in a more fine-grained manner, two pins at a
time. Each pin pair will have one of four functions:
function
number
| description
|
0
| GPIO
|
1
| ISA
|
2
| reserved
|
3
| reserved
|
Setting
the function of each pair of pins is done by writing the function
number to the appropriate pair of bits in the register corresponding to
the row in question. The table below shows the bit positions in
each register on the top row, while the cells below in the same column
give the corresponding pin numbers for each row which are programmed
with those bits at the specified register address.
row
| register
adrs\/ bits->
| 31
30
| 29
28
| 27
26
| 25
24
| 23
22
| 21
20
| 19
18
| 17
16
| 15
14
| 13
12
| 11
10
| 09
08
| 07
06
| 05
04
| 03
02
| 01
00
|
A
| 0xE8000030
| 32
31
| 30
29
| 28
27
| 26
25
| 24
23
| 22
21
| 20
19
| 18
17
| 16
15
| 14
13
| 12
11
| 10
09
| 08
07
| 06
05
| 04
03
| 02
01
|
B
| 0xE8000034
| 32
31
| 30
29
| 28
27
| 26
25
| 24
23
| 22
21
| 20
19
| 18
17
| 16
15
| 14
13
| 12
11
| 10
09
| 08
07
| 06
05
| 04
03
| 02
01
|
C
| 0xE8000038
|
|
|
|
|
|
| 19
18
| 17
16
| 15
14
| 13
12
| 11
10
| 09
08
| 07
06
| 05
04
| 03
02
| 01
00
|
D
| 0xE800003C
|
|
|
|
|
|
| 19
18
| 17
16
| 15
14
| 13
12
| 11
10
| 09
08
| 07
06
| 05
04
| 03
02
| 01
00
|
For
example, from the above table we can see that to set the function of
pins B19 and B20 we would write the function number to bits [19:18] of
the register at address 0xE8000034. We can tell this because when
we look at the "B" row we see "20 19" in the cell whose column is
headed by "19 18".
The function of the PC-104 connector pins are
given in the table below. The "ISA" column gives the name of the
pin signal when it is configured as ISA, while the "GPIO" column gives
the name of the pin signal when it is configured as GPIO. To save
space, there are two sets of columns in each table, whereby the pin
name is listed first, followed by the ISA signal and then the GPIO
signal, and then this order is repeated for the other set of pins on
the same physical header. The 64-pin connector is given first:
pin
| ISA
| GPIO
| pin
| ISA
| GPIO
|
A1
| IOCHK#
| A[0]
| B1
| GND
| GND
|
A2
| D7
| A[1]
| B2
| RESET
| B[1]
|
A3
| D6
| A[2]
| B3
| +5V
| +5V
|
A4
| D5
| A[3]
| B4
| IRQ9
| B[3]
|
A5
| D4
| A[4]
| B5
| 3.3V
| 3.3V
|
A6
| D3
| A[5]
| B6
| DRQ2
| B[5]
|
A7
| D2
| A[6]
| B7
| NC
| B[6]
|
A8
| D1
| A[7]
| B8
| ENDX#
| B[7]
|
A9
| D0
| A[8]
| B9
| 8V_30V
| 8V_30V
|
A10
| IORDY
| A[9]
| B10
| GND
| GND
|
A11
| AEN
| A[10]
| B11
| MEMW#
| B[10]
|
A12
| A19
| A[11]
| B12
| MEMR#
| B[11]
|
A13
| A18
| A[12]
| B13
| IOW#
| B[12]
|
A14
| A17
| A[13]
| B14
| IOR#
| B[13]
|
A15
| A16
| A[14]
| B15
| DACK3#
| B[14]
|
A16
| A15
| A[15]
| B16
| DRQ3
| B[15]
|
A17
| A14
| A[16]
| B17
| DACK1#
| B[16]
|
A18
| A13
| A[17]
| B18
| DRQ1
| B[17]
|
A19
| A12
| A[18]
| B19
| RFRSH#
| B[18]
|
A20
| A11
| A[19]
| B20
| BCLK
| B[19]
|
A21
| A10
| A[20]
| B21
| IRQ7
| B[20]
|
A22
| A9
| A[21]
| B22
| IRQ6
| B[21]
|
A23
| A8
| A[22]
| B23
| IRQ5
| B[22]
|
A24
| A7
| A[23]
| B24
| IRQ4
| B[23]
|
A25
| A6
| A[24]
| B25
| IRQ3
| B[24]
|
A26
| A5
| A[25]
| B26
| DACK2#
| B[25]
|
A27
| A4
| A[26]
| B27
| TC
| B[26]
|
A28
| A3
| A[27]
| B28
| BALE
| B[27]
|
A29
| A2
| A[28]
| B29
| +5V
| +5V
|
A30
| A1
| A[29]
| B30
| OSC
| B[29]
|
A31
| A0
| A[30]
| B31
| GND
| GND
|
A32
| GND
| GND
| B32
| ISA_B32
| B[31]
|
Here are the pin assignments for the 40-pin connector.
pin
| ISA
| GPIO
| pin
| ISA
| GPIO
|
C0
| GND
| GND
| D0
| GND
| GND
|
C1
| SBHE#
| C[1]
| D1
| MEM16#
| D[1]
|
C2
| LA23
| C[2]
| D2
| IO16#
| D[2]
|
C3
| LA22
| C[3]
| D3
| IRQ10
| D[3]
|
C4
| LA21
| C[4]
| D4
| IRQ11
| D[4]
|
C5
| LA20
| C[5]
| D5
| IRQ12
| D[5]
|
C6
| LA19
| C[6]
| D6
| IRQ15
| D[6]
|
C7
| LA18
| C[7]
| D7
| IRQ14
| D[7]
|
C8
| LA17
| C[8]
| D8
| 3.3V
| 3.3V
|
C9
| MEMR#
| C[9]
| D9
| DRQ0
| D[9]
|
C10
| MEMW#
| C[10]
| D10
| DACK5#
| D[10]
|
C11
| SD8
| C[11]
| D11
| DRQ5
| D[11]
|
C12
| SD9
| C[12]
| D12
| DACK6#
| D[12]
|
C13
| SD10
| C[13]
| D13
| DRQ6
| D[13]
|
C14
| SD11
| C[14]
| D14
| DACK7#
| D[14]
|
C15
| SD12
| C[15]
| D15
| DRQ7
| D[15]
|
C16
| SD13
| C[16]
| D16
| +5V
| +5V
|
C17
| SD14
| C[17]
| D17
| MASTER#
| D[17]
|
C18
| SD15
| C[18]
| D18
| GND
| GND
|
C19
| GND
| GND
| D19
| GND
| GND
|
Note: The GPIO nomenclature in these tables is such that, for example, "A[0]" means "Bit 0 of GPIO Register A", and in general "X[n]" means "Bit n of GPIO Register X" and "X[n:m]" means "Bits n through m of GPIO register X", where X is one of A, B, C, or D.
PC-104 bus
The
TS-7800 provides control over some of the ISA parameters of the PC-104
bus through a 32-bit register located at address 0xE800000C, which is
defined as follows:
bit(s)
| function
|
5-0
| ISA strobe length
|
9-6
| ISA setup length
|
10
| Honor ISA 0WS/ENDX signal (1=true)
|
11
| TS special ISA pinout enable (1=true)
|
12
| ISA oscillator select
0
| high-jitter approximation of 14.318Mhz
| 1
| clean 25Mhz
|
|
(Other bits in this register should be masked out.)
The ISA strobe length and ISA setup length are both given as the number of extra 10ns periods.
The
ISA strobe length is the amount of addition time that ISA_IOR, ISA_IOW,
ISA_MEMR, and ISA_MEMW are held asserted. The minimum (when
bits are zero) is 20ns. The default power-on value is 40, for a
420ns strobe length. If configured to honor the ISA 0WS/ENDX
signal, the peripheral will skip the remaining strobe time for an early
transaction end, allowing for faster devices then standard ISA allows.
The
ISA setup length is the additional amount of time above 20ns that the
address and data are held stable before asserting the strobe. The
default is 14 (160ns).
There is an additional 20ns hold time at
the end of the strobe where address and data are kept valid. The
default total bus cycle length is then 160ns (setup) plus 420ns
(strobe) plus 20ns (hold) for a total of 500ns (2Mhz). This is
very conservative for modern hardware and most designs can actually run
much faster.
Bus Addresses
To access peripherals on the
PC104 bus it is necessary to add the base address from the table below
to the offset of the peripheral to get a memory address for accessing
the peripheral. For example, for ISA 8-bit I/O address 0x100, add
0xEE00_0000 to 0x100 to get 0xEE00_0100.
| memory
| I/O
|
8-bit
| 0xEC00_0000
| 0xEE00_0000
|
16-bit
| 0xED00_0000
| 0xEF00_0000
|
UARTs
The
TS-7800 has twelve UARTs. Two of these UARTs, which appear on the
COM1 (DB9) header and the COM2 (10-pin) header are driven by the CPU.
The other ten UARTs are TS-UARTs driven by the FPGA.
When
some TS-UART ports are enabled, they override the meanings of other
pins with their own meanings. When disabled, the pins revert to
their original meaning. The table below describes the ten TS-UART
ports. The "RS-" column indicates whether the port is RS-232,
RS-485/422, or TTL. The "base adrs" column indicates the address
of the STAT register; the DATA register is offset +2 from that.
All TS-UART registers must be accessed through 16-bit memory
access. The "header" column indicates which header the port is
located on, and the "Tx", "Rx", "TxEn", "RTS", and "CTS" indicate the
pin number of those respective signals on the header specified.
#
| RS-
| base adrs
| header
| Tx
| Rx
| TxEn
| RTS
| CTS
|
0
| 232
| 0xE80000C0 | COM1
| 7
| 8
| N/A | no | no |
1
| 232
| 0xE80000C4 | COM1
| 4
| 1
| N/A | no | no |
2
| 485
/
422
| 0xE80000C8 | COM2
| +:6
-:1
| +:4
-:9(1)
| N/A | no | no |
3
| 485
| 0xE80000CC | COM2
| +:4
-:9(2)
| N/A
| N/A | no | no |
4
| 232
| 0xE80000D0 | COM3
| Tx
| Rx
| N/A | RTS
| CTS
|
5
| 232
| 0xE80000D4 | COM3
| 7
| 8
| N/A | N/A | no |
6
| TTL
| 0xE80000D8 | DIO
| 13
| 15
| 11
| N/A | no |
7
| TTL
| 0xE80000DC | LCD
| 13
| 14
| 12
| N/A | no |
8
| TTL
| 0xE80000E0 | PC-104
| C18
| C19
| C17
| N/A | no |
9
| TTL
| 0xE80000E4 | PC-104
| C15
| C16
| C14
| N/A | N/A |
(1) only if RS-422 is selected by setting bit 15 of register 0xE800000C
(2) only if RS-485 is selected by clearing bit 15 of register 0xE800000C
All
TS-UARTs can be run at one of 7 programmable baud rates, access as baud
rate indicies 0-6. These baud rates are programmable by accessing
the 16-bit address for the index of interest. The baud rate
index corresponds to the value written into the TS-UART STAT register's
baud rate bits to select that speed. (Note: a baud rate index of 7 is
reserved in the TS-UART to mean "disabled".)
baud index
| register address
|
0
| 0xE80000E8
|
1
| 0xE80000EA |
2
| 0xE80000EC |
3
| 0xE80000EE |
4
| 0xE80000F0 |
5
| 0xE80000F2 |
6
| 0xE80000F4 |
The value of the register can be computed from the following formula:
100,000,000 / (8 * baud_rate)
TS-UART
The
TS-UART design used in the TS-7800 is fundamentally the same as the
TS-UARTs in other TS boards. The TS-UART is a compact, two
register design created to require minimal space in an FPGA. The
two registers are STAT and DATA. The layout of the STAT register
is:
bit(s)
| name
| A
| function
|
0
| TBRE
| RO
| transmit buffer
not full
|
1
| DR
| RO
| receive data ready
|
2
| OERR
| RO
| receive overflow
|
3
| CTS
| RO
| UART CTS
|
4
| RTS
| RW
| UART RTS
|
7:5
| BAUD
| RW
| baud rate index
defaults to:
0
| 115200
| 1
| 57600
| 2
| 38400
| 3
| 19200
| 4
| 9600
| 5
| 4800
| 6
| 2400
| 7
| OFF
|
|
8
| NINEBIT
| RW
| enable 9-bit mode
|
9
| RBREAK
| RO
| BREAK detected
|
10
| TBREAK
| RW
| transmit BREAK
|
11
| DMXS
| RO
| Reserved
|
12
| TRE
| RO
| transmitter empty
|
13
| SLOW
| X
| Reserved
|
15:14
| N/A
| X
| Reserved
|
Please
consult the driver source code files tsuart1.c and tsuart-7800.c for
more information on implementing a device driver for the TS-UART on the
TS-7800.
GPIO on PC-104 connector
The PC-104
connector can be multiplexed between PC-104 functionality and GPIO
functionality. There are up to 89 general purpose digital I/O
pins available. This corresponds to 104 pins total minus fifteen pins
carrying power or ground rails.
Each GPIO pin has a two
corresponding register bits, one in the GPIO data register, and one in
the GPIO direction register. The data register, when read,
contains the current state of all pins in GPIO mode. When
written, the value written will determine the state of all pins in GPIO
mode, but only for pins which have their direction set to "output".
The GPIO register map follows:
address
| row
| register
|
0xE8000010
| A
| data
|
0xE8000014
| B
| data
|
0xE8000018
| C
| data
|
0xE800001C
| D
| data
|
0xE8000020
| A
| direction
|
0xE8000024
| B
| direction |
0xE8000028
| C
| direction |
0xE800002C
| D
| direction |