TS7250 to TS7260 CPLD changes
====================

* New TS7260 specific 8-bit register at 0x12000000 physical space.

   bit 0: RS232 level converter power (1 - on, 0 - off)
   bit 1: USB 5V power
   bit 2: LCD header 5V power
   bit 3: 5V switcher enable (only setable if JP7 OFF)
   bit 4: PC104 clock disable (1 - clock disabled)
   bit 5: PC104 fast strobes (1 - enabled)
   bit 6: TTL uart enable (1 - COM3 switched to TTL on DIO3 header)
   bit 7: scratch register (retains state during reboots)

  * 5V switcher will default to on / '1' if board is powered up with JP7 OFF.  If board is powered up with JP7 on, this bit is stuck '0'.  It is not recommended changing this bit during normal operation.

  * Scratch register is intended to be used by watchdog software to determine if last reboot was result of watchdog expiry (value '1'), or normal system reboot or power-on (value '0')

  * PC104 fast strobes bit allows for non-ISA compatible, but much faster bus cycle timing for custom boards.  Contact Technologic Systems for more information.  Bit should remain '0' for normal PC104 bus operation.

 *  When TTL uart enable bit is set, COM3 RS232 signals RX and TX on the COM3 header are ignored and instead appear on pins 0 (TX) and 2 (RX) on the DIO3 header as 3.3V TTL signals.  This will override any settings for those pins in the DIO registers.

* Least significant three bits of model register at 0x22000000 are '010' (decimal 2 - TS7260 unique code)

* Bit 0 of options register (previously ADC option bit) now refers to whether or not the CPLD is loaded with the 5 UART option (1), or TS-XDIO option (0).


COM3 port details
=============

The COM3 serial port is implemented off CPU on the board CPLD chip at address 0x12400000. It has a 5 byte receive fifo and a 1 byte transmit FIFO.  There exists a Linux serial driver "tsuart" which allows manipulation of this hardware in Linux using the device node /dev/ttyTS0.  The 5 byte receive FIFO is enough to prevent buffer overflow at 115200 baud with the Linux driver, but it is recommended to give first priority to using the on-CPU COM1 or COM2 ports with 16-byte FIFOs at these high speeds.

The TS-UART is only capable of 8N1 type serial communications which is 1 start bit, 8 data bits, no parity, and 1 stop bit.  7 bits + even or odd parity is also possible (by computing/checking parity in software). Other formats such as 9-bit serial are possible with custom CPLD loads.  Contact Technologic Systems for more information regarding this.

 address 0: STAT register
   bit 0 - TBRE, Transmit buffer empty (RO)
   bit 1 - DR, Receive data ready (RO)
   bit 2 - OERR, Overflow error (RO)
   bit 3 - CTS, UART clear-to-send (RO)
   bit 4 - RTS, UART request-to-send (RW)
   bit 7:5 - MODE, baud rate (RW)
      0 - 115200 8N1
      1 - 57600 8N1
      2 - 38400 8N1
      3 - 19200 8N1
      4 - 9600 8N1
      5 - 4800 8N1
      6 - 2400 8N1
      7 - UART off, IRQ disabled
 read address 1: RXDAT register (RX data register)
 write address 1: TXDAT register (TX data register)

* The UART core will interrupt the CPU while there is data in the RX fifo and on the rising edge of the TBRE bit. (full -> empty transition).  The IRQ is cleared on read of the STAT register


5 UART option
==========

The TS-7260 may be built with either the TS-XDIO port or two more TTL-only COM ports.  If the board was built with the 5 COM port option, the 4th and 5th COM ports appear at addresses 0x13000000 (COM4) and 0x13400000 (COM5).  When these UARTs are not off, (MODE register is not 7) they appear on the DIO3 header as follows:

  COM4:
    tx: DIO3 pin 5
    rx: DIO3 pin 7
  COM5:
    tx: DIO3 pin 9
    rx: DIO3 pin 11 

When the UARTs are off (MODE register is 7), these pins are GPIO pins.  Though there is not enough logic space available on the CPLD for the 5 uart option and the TS-XDIO GPIO core, there is a simple GPIO core without all the TS-XDIO functionality implemented at 0x12c00000.

address 0: data register (1 - pin at logic high, 0 - logic low)
address 1: data direction register (1 - output, 0 - input)

* bit X of each register corresponds to pin X * 2 + 1 on the DIO3 header.

Hardware changes:  
=================================

* internal ep9302 ADC channels routed to monitor incoming power supply voltage,  1.8V supply,
  and 5V supply and not brought out on header.

* Board is slightly longer than TS-7250

* JP8 jumpers external power to PC104 traditional 12V pin

* JP9 OFF keeps ethernet LED's off.

* MAX197 ADC option is NOT available