TS MACROCONTROLLER EXTERNAL BUS (MUXBUS) All TS-4xxx TS_SOCKET macrocontoller COMs have an external bus called the MUXBUS. The bus consists of 16 muxed address/data lines, ALE#, CS#, DIR, BHE#, and WAIT#. The MUXBUS provides a way for TS-SOCKET base board designers to include static memory devices, bridges to other industry standard buses such as PC/104, or an FPGA that implements custom features. Verilog modules ts8100.v and muxbusbridge.v are provided as examples of how to interface with the MUXBUS. The bus cycle speed depends on the FPGA clock speed, which varies from one macrocontroller to another. Thus, the MUXBUS behavior is specified in clock cycles. The bus cycle is as follows: 1. ALE# asserted, the address is driven on the bus lines. This condition is held for TP_ALE + 1 clock cycles. 2. ALE# is de-asserted while the address remains valid for TH_ADR + 1 clock cycles. 3. Data is driven on the bus lines (for a write) or the bus lines go high-Z (for a read) for TSU_DAT + 1 clock cycles. 4. CS# is asserted for TP_CS + 1 clock cycles. 5. CS# is de-asserted and Data remains valid for TH_DAT + 1 clock cycles. BHE# and DIR remain valid through the whole bus cycle. WAIT# is an input. The external device can assert the WAIT signal during the CS pulse to extend it. The bus can work in 8 bit or 16 bit modes. In 8 bit mode, mux lines 8-15 are not used for data and BHE# is ignored. In 16 bit mode, byte reads and writes are still supported using BHE# and A0. Each module will have a 16 bit external bus configuration register in its syscon. The format of that register is as follows: bit 0 = bus enable (otherwise, pins are GPIO or reserved) bits 2:1 = TP_ALE bits 4:3 = TH_ADR bits 6:5 = TSU_DAT bits 12:7 = TP_CS bits 15:13 = TH_DAT A TP_CS of 0x3f is not supported -- use a value from 0 to 62. Currently the clock cycle times are: TS-4500: 13.33 ns TS-4200: 20.20 ns TS-4700: 10.00 ns TS-4800: 10.42 ns TS-4200 USAGE: -------------- Unlike most modules, the TS-4200 only provides 10 bits of MUXBUS address space. The TS-4200 bus config register is at address 0x30000020. After the bus is enabled, the 16 bit MUXBUS base address is 0x30000400 and the 8 bit base address is 0x10000400. TS-4700 USAGE: -------------- The TS-4700 provides 15 bits of MUXBUS address space. The TS-4700 bus config register is at 0x80004004. After the bus is enabled, the 16 bit MUXBUS base address is 0x80008000 and the 8 bit base address is 0x81008000. TS-4500 USAGE: -------------- The TS-4500 provides a full 16 bits of MUXBUS address space. The TS-4500 does not ship with an FPGA load that supports the MUXBUS, but if a bitstream built from the recent opencore project is loaded, it is supported. Since the TS-4500 SBUS space is very limited, the opencore uses a memory window to provide muxbus address space. The bus config register is at offset 0x20000 in memwindow space. After the bus is enabled, the 16 bit MUXBUS base address is at offset 0x0 in memwindow space, and the 8 bit MUXBUS base address is at offset 0x10000. A recent version of sbus.c provides functions that abstract away the memory window. The TS-4500 does not have a BUS_WAIT# line, so it is important to provide a TP_CS such that the responding device will have plenty of time. TS-8100/TS-8160 INFORMATION: ---------------------------- The TS-81xx boards decode 10 bits of MUXBUS address. The address space is divided as follows: 0x0 to 0xf: TS-8100 registers 0x10 to 0xff: Reserved 0x100 to 0x3ff: PC/104 space The PC/104 bus only supports 8 bit peripherals. Thus, only 8 bit bus cycles should be used to access that region. The base address for the peripheral should be added to the MUXBUS base address, not to 0x100. Thus PC/104 peripherals with a base address below 0x100 (which is not normal) are not supported. The TS-8100 registers are 16 bit registers and must be accessed with 16 bit cycles. Here is the TS-81xx CPLD register map: * Offset Usage * 0x0 Board ID: read 0x8100 * 0x2 Control register: * bits 3:0 PLD revision * bits 7:4 LCD contrast * bits 15:8 control register: * bit 8: USB reset * bit 9: ISA reset * bit 10: enable oscillator * bit 11: enable RS-232 * bit 12: enable LCD power * bit 13: CAN1 standby * bit 14: CAN2 standby * bit 15: LCD contrast enable * 0x4 DIO output data * 0x6 LCD/AVR output data * bit 11: AVR MOSI * bit 12: AVR SCLK * bit 13: AVR RESET * 0x8 DIO DDR * 0xA LCD DDR * 0xC DIO input data * 0xE LCD/AVR input data * bit 11: AVR MISO * * DIO registers: * bits 7:0 are odd numbered pins 15:1 on the DIO header * bits 13:8 are PC/104 pins A21:A16 * bits 15:14 are PC/104 pins B12:B11 * * LCD registers: * bits 7:0 are data lines (pins 14:7) * bit 8 is LCD WR# (pin 6) * bit 9 is LCD RS (pin 3) * bit 10 is LCD EN (pin 5) * higher bits should be zero during LCD manipulations.