/* Copyright 2007, Unpublished Work of Technologic Systems * All Rights Reserved. * * THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL, * PROPRIETARY AND TRADE SECRET INFORMATION OF TECHNOLOGIC SYSTEMS. * ACCESS TO THIS WORK IS RESTRICTED TO (I) TECHNOLOGIC SYSTEMS * EMPLOYEES WHO HAVE A NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE * OF THEIR ASSIGNMENTS AND (II) ENTITIES OTHER THAN TECHNOLOGIC * SYSTEMS WHO HAVE ENTERED INTO APPROPRIATE LICENSE AGREEMENTS. NO * PART OF THIS WORK MAY BE USED, PRACTICED, PERFORMED, COPIED, * DISTRIBUTED, REVISED, MODIFIED, TRANSLATED, ABRIDGED, CONDENSED, * EXPANDED, COLLECTED, COMPILED, LINKED, RECAST, TRANSFORMED, ADAPTED * IN ANY FORM OR BY ANY MEANS, MANUAL, MECHANICAL, CHEMICAL, * ELECTRICAL, ELECTRONIC, OPTICAL, BIOLOGICAL, OR OTHERWISE WITHOUT * THE PRIOR WRITTEN PERMISSION AND CONSENT OF TECHNOLOGIC SYSTEMS. * ANY USE OR EXPLOITATION OF THIS WORK WITHOUT THE PRIOR WRITTEN * CONSENT OF TECHNOLOGIC SYSTEMS COULD SUBJECT THE PERPETRATOR TO * CRIMINAL AND CIVIL LIABILITY. */ /* System controller containing misc regs and functionality including: * - Board and FPGA revision identification registers * - ISA/PC104 bridge control (timing, features, etc..) * - PC104 GPIO in/out/dir registers * - PC104 pin muxing between different functions (uart, isa, gpio) * - 10 TS-UARTs (16-bit with 16-byte TX/RX FIFOs) * - 7 programmable baud rate generators to feed into the TS-UARTs * - 32-bit hardware random number generator * - 32-bit free-running microsecond counter * - LCD and DIO header GPIO logic * - Green LED control, temperature sensor SPI chip-select, and * jumper (JP1, JP2) settings. * * On the default TS-7800 load, this core sits behind the WB slow bus * running at 25Mhz. In the 2.6 Linux TS provides, the base physical * address is 0xe8000000. * * Register map: * base + 0x0: Board identification (RO) * bit 7-0: FPGA revision (must be greater than 0) * bit 31-8: Board magic (must be 0x??????) * base + 0x4: LCD/DIO input and jumper status (RO) * bit 15-0: DIO header data in (LSB - pin 1, MSB - pin 16) * bit 29-16: LCD header data in (LSB - pin 1, MSB - pin 14) * bit 30: JP1 status (1 - on) * bit 31: JP2 status (1 - on) * base + 0x8: LCD/DIO output and LED/temp sensor control (R/W) * bit 15-0: DIO header data out reg (LSB - pin 1, MSB - pin 16) * bit 29-16: LCD header data out reg (LSB - pin 1, MSB - pin 14) * bit 30: green LED (1 - on) * bit 31: temp sensor chipselect (1 - selected) * * * LCD/DIO header is open-drain with pullups-- you can drive low, but * a 1 only tri-states. This header is 5V tolerant. * * * base + 0xc: ISA control and UART control (R/W) * bit 5-0: ISA strobe length (number of extra 10nS periods) * bit 9-6: ISA setup length (number of extra 10nS periods) * bit 10: Honor ISA 0WS/ENDX signal (1 - honor 0WS) * bit 11: TS special ISA pinout enable * bit 12: ISA oscillator select * 0 - OSC PC104 signal is a high-jitter approximation of 14.318Mhz * 1 - OSC PC104 signal is a clean 25Mhz * bit 13: UART RTS for COM1 header (first CPU serial port) * bit 14: UART DTR for COM1 header (first CPU serial port) * bit 15: RS485/RS422 control * 1 - single RS422 using TS-UART#2 on COM2 header * 0 - dual RS485 using TS-UART#2 and TS-UART#3 * bit 16: UART RTS for COM3 header * bit 31-17: reserved * * * ISA strobe length is the additional amount of time the ISA_IOR, * ISA_IOW, ISA_MEMR, and ISA_MEMW is held asserted. The minimum * (w/register = 0) is 20nS. The default power-on value is 40, for a * 420 nS strobe length. If configured to honor the ISA ENDX/0WS * signal (bit 10, reg 0xc), the peripheral will skip the remaining * strobe time for an early transaction end-- allowing for faster * devices than standard ISA on the bus. * * * ISA setup length is the additional amount of time above 20nS * the address and data are held stable before asserting the strobe. * The default is 14, for 160nS. * * * There is an additional 20nS hold time at the end of the strobe * where address and data are kept valid. The default total bus cycle * length is then 160nS (setup) + 420nS (strobe) + 20nS (hold) or * 500nS (2Mhz). This is very conservative for modern hardware and * most designs can actually run much faster. * * * The RS485/RS422 control reg allows either 1 full-duplex RS422 * port on TS-UART#2, or 2 half-duplex RS485 ports on TS-UART#2 and * TS-UART#3. When using RS422, TS-UART#3 should not be used. The * singe RS422 port uses pins 6 and 1 for TX and 4 and 9 for RX on * the COM2 header. When using dual RS485, TS-UART#2 uses pins 6 * and 1; TS-UART#3 uses pins 4 and 9. * * * base + 0x10: PC104 A GPIO in/out reg (R/W) * bit 31-0: pin input/output (MSB - pin A32, LSB - pin A1) * base + 0x14: PC104 B GPIO in/out reg (R/W) * bit 31-0: pin input/output (MSB - pin B32, LSB - pin B1) * base + 0x18: PC104 C GPIO in/out reg (R/W) * bit 19-0: pin input/output (MSB - pin C20, LSB - pin C1) * bit 31-20: reserved * base + 0x1c: PC104 D GPIO in/out reg (R/W) * bit 19-0: pin input/output (MSB - pin D20, LSB - pin D1) * bit 31-20: reserved * base + 0x20: PC104 A GPIO direction reg (R/W) (1 - output) * bit 31-0: pin direction (MSB - pin A32, LSB - pin A1) * base + 0x24: PC104 B GPIO direction reg (R/W) (1 - output) * bit 31-0: pin direction (MSB - pin B32, LSB - pin B1) * base + 0x28: PC104 C GPIO direction reg (R/W) (1 - output) * bit 19-0: pin direction (MSB - pin C20, LSB - pin C1) * bit 31-20: reserved * base + 0x2c: PC104 D GPIO direction reg (R/W) (1 - output) * bit 19-0: pin direction (MSB - pin D20, LSB - pin D1) * bit 31-20: reserved * * * PC104 pin numbering is not like GPIO/LCD header pin numbering. * Row A is the XXX: TODO * * * base + 0x30: PC104 A MUX reg (R/W) * bit 1-0: MUX function select for pins A1-A2 * 0 - GPIO * 1 - ISA * 2 - reserved * 3 - reserved * bit 3-2: MUX function select for pins A3-A4 * 0 - GPIO * 1 - ISA * 2 - reserved * 3 - reserved * bit 5-4: MUX function select for pins A5-A6 * ... * bit 31-30: MUX function select for pins A31-A30 * base + 0x34: PC104 B MUX reg (R/W) * base + 0x38: PC104 C MUX reg (R/W) * base + 0x3c: PC104 D MUX reg (R/W) * * * Each pair of pins can be individually used for one of * 4 functions. 2-bits in the above registers in the above * MUX regs are used to select which for each respective pair. * * * base + 0x40: free-running microseconds counter (RO) * base + 0x44: 32 bits of random data changed every 1 second. (RO) * base + 0xc0: TS-UART#0 stat reg (16-bit reg) * base + 0xc2: TS-UART#0 data reg (16-bit reg) * base + 0xc4: TS-UART#1 stat reg (16-bit reg) * base + 0xc6: TS-UART#1 data reg (16-bit reg) * ... * base + 0xe4: TS-UART#9 stat reg (16-bit reg) * base + 0xe6: TS-UART#9 data reg (16-bit reg) * * * TS-UART#0 uses COM1 header RTS (pin 7) and CTS (pin 8) for * RS232 TX and RX respectively. * * * TS-UART#1 uses COM1 header DTR (pin 4) and DCD (pin 1) for * RS232 TX and RX respectively. * * * TS-UART#2 is a RS485/RS422 UART. If bit 15, reg 0xc is clear, * RS485 is selected and RS485 +/- are on the COM2 header, pins 6 * and 1 (traditionally DSR and DCD). If bit 15, reg 0xc is set, * RS422 is selected and the TX +/- is as above, but the RX +/- * pair is on pins 4 and 9 (traditionally DTR and RI). * * * TS-UART#3 is only enabled if bit 15, reg 0xc is clear. It uses * COM2 header pins 4 and 9 (traditionally DTR and RI) as a * half-duplex RS485 UART. * * * TS-UART#4 is a RS232 UART on the COM3 header. If TS-UART#5 is * not enabled, the RTS and CTS lines can be used for flow control * by manipulating bit 16, reg 0xc for RTS and bit 17, reg 0xc for * CTS. XXX: TODO * * * TS-UART#5 is a RS232 UART that uses the RTS and CTS flow control * signals on the COM3 header. When enabled, bit 16 reg 0xc has no * effect on the header as it is used instead as this UART's TX * signal. * * * TS-UART#6 is a TTL UART that when enabled, overrides the GPIO * configuration for the DIO header pins 13 and 15, and uses them * for TX and RX, respectively. DIO header pin 11 is also hijacked * as a transmit enable that goes high whenever the UART is * transmitting a character. * * * TS-UART#7 is a TTL UART that when enabled, overrides the GPIO * configuration for the LCD header pins 13 and 14, and uses them * for TX and RX, respectively. LCD header pin 12 is also hijacked * as a transmit enable that goes high whenever the UART is * transmitting a character. * * * TS-UART#8 is a TTL UART that uses PC104 connector pins C19 (RX), * C18 (TX), and C17 (TXEN). The multiplexor function for these pins * (bits 19-18, and 17-16 reg 0x38) should be set to GPIO (0x0). * * * TS-UART#9 is a TTL UART that uses PC104 connector pins C16 (RX), * C15 (TX), and C14 (TXEN). The multiplexor function for these pins * (bits 15-14, and 13-12 reg 0x38) should be set to GPIO (0x0). * * base + 0xe8: Baudrate generator timer #0 (16-bit) * base + 0xea: Baudrate generator timer #1 (16-bit) * base + 0xec: Baudrate generator timer #2 (16-bit) * base + 0xee: Baudrate generator timer #3 (16-bit) * base + 0xf0: Baudrate generator timer #4 (16-bit) * base + 0xf2: Baudrate generator timer #5 (16-bit) * base + 0xf4: Baudrate generator timer #6 (16-bit) * * * Baudrate generators run at 100Mhz. Prescalar should be chosen to * match 8x desired baud rate as close as possible. Each timer * number corresponds to the value written to the clock select bits of * each TS-UART stat register. Writing a value of 0x7 is reserved in * the TS-UARTs to mean UART is disabled. All TS-UARTs share these same * 7 baudrate timers. * */