/* Copyright 2007, Unpublished Work of Technologic Systems
  * All Rights Reserved.
  *
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/* NAND flash controller with hardware Hamming-code ECC generator.
  * ECC generator has 8 entry FIFO to allow for streaming of an entire
  * 2 kbyte page while saving and reseting the ECC syndrome every 256
  * bytes.
  *
  * Register map:
  * base + 0x0: NAND control and ECC register
  *   bit 0: ALE, address latch enable bit (1 - asserted)
  *   bit 1: CLE, command latch enable bit (1 - asserted)
  *   bit 2: CS, chip select (1 - asserted)
  *   bit 3: ECC fifo enable
  *   bit 4: FIFO last or FIFO empty (RO)
  *   bit 5: NAND chip busy, (1 - busy) (RO)
  *   bit 7-6: reserved
  *   bit 31-8: Hamming code ECC bits
  * base + 0x4: NAND data register
  * base + 0x8: RTC address register
  * base + 0xc: RTC data register
  *
  * * When FIFO is enabled, bits 31-8 of register 0x0 return enqueued
  *   ECC bits until a read with bit 4 set.  When bit 4 is set, the
  *   read ECC bits are valid, but the FIFO is now empty and further
  *   reads will be UNDEFINED.
  *
  * * If the FIFO is not enabled, bits 31-8 of register 0x0 will return
  *   current ECC state.
  *
  * * Reads or writes to bits 31-8 of register 0x0 will advance the FIFO
  *   (if FIFO is enabled) and reset ECC state.
  *
  * * A 32-bit read at the data register will cause 4 NAND RD# cycles
  *   and return the 4 bytes as a little endian (LSB first) word.  A
  *   16-bit read will return 2 cycles, and a 8-bit 1.  8-bit and
  *   16-bit reads must only be to base + 0x4 address, reads/writes
  *   to base + 5, 6, 7 are UNDEFINED.
  *
  * * RTC registers are 8-bit only.
  */