/* Copyright 2007, Unpublished Work of Technologic Systems
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/* Core to automatically transfer data between 2 masters.  To use,
  * first setup control register.  DMA operation will proceed on master
  * interfaces with asserted drq_i signal only when the DMA length field
  * in the control register is non-zero.  When DMA operation is done,
  * the dack_o will be asserted on the completed master interface(s).
  *
  * Register map:
  * base + 0x0: DMA control register (R/W)
  *   bits 11:0 - DMA length (number of transfers, not necessarily bytes)
  *   bit 12 - DMA direction (0 - wbm1 reads, 1 - wbm2 reads)
  *   bits 15:13 - wbm2 address increment per transfer
  *   bits 18:16 - wbm1 address increment per transfer
  *   bits 20:19 - DMA transfer size
  *     0 - 1 byte
  *     1 - 2 bytes (halfwords)
  *     2 - 4 bytes (words)
  *     3 - reserved
  *   bits 29:21 - reserved
  *   bit 30 - DRQ1 input (wbm1 is ready for DMA)
  *   bit 31 - DRQ2 input (wbm2 is ready for DMA)
  * base + 0x4: wbm1 address (R/W) - must be transfer size aligned
  * base + 0x8: wbm2 address (R/W) - must be transfer size aligned
  *
  * When DMA operation starts:
  *   - dack_o signal negedge
  *
  * When DMA operation is in progress:
  *   - dack_o signals will be low
  *   - DMA length (bits 11:0 in DMA control reg) will be decrementing
  *     to zero.
  *   - wbm1 address and wbm2 address regs will be incrementing as
  *     configured in bits 18:13 of the DMA control reg
  *
  * When DMA operation completes:
  *   - dack_o signal posedge
  *   - DMA length (bits 11:0 in DMA control reg) will be zero.
  *   - wbm1 address and wbm2 address regs will be pointing at the
  *     ending address plus 1 address increment (bits 18:13)
  *
  * When DMA is idle:
  *   - dack_o signal is high
  */