TS-4500 OPENCORE WITH GENERAL PURPOSE MEMWINDOW AND EXTERNAL BUS

/* This core is a simple core to allow access to an up to 128Mbyte WISHBONE
 * address space via a 4 16-bit register window.  It allows arbitrary mixing/
 * matching of WISHBONE slaves bus width (8/16/32) and has some optimization
 * features to minimize superfluous cycles typical to accessing via a window.
 *
 * This core's first use was on the TS-4500 to access the much larger address
 * space of ISA for the TS-8100 base board.
 *
 * Register map:
 * base + 0x0: Upper address reg, address bits 26-11 (RW)
 * base + 0x2: WISHBONE config reg (RW)
 *   bit 15-14: bus width
 *     0 - reserved
 *     1 - 32 bit
 *     2 - 16 bit
 *     3 - 8 bit
 *   bit 13-12: Data reg #2 config (RW)
 *     0 - normal
 *     1 - two-cycle split (16bit in -> 2x 8bit cycles out)
 *     2 - two-cycle combine (2x 16bit cycles -> 32bit cycle)
 *     3 - combo adr/data write (8 LSBs: data, 8 MSBs: override 8 LSBS of adr)
 *   bit 11: Data reg #2 auto-increment enable
 *   bit 10-0: lower address reg, address bits 10-0
 *
 * * Two-cycle combine reads/writes should first read/write the lower (LSB)
 *   address to properly be combined.  The address is always auto-incremented.
 *
 * * After a combo adr/data write cycle, the address reg points to the address
 *   that was previously written with optional auto-increment by 1.
 *
 * base + 0x4: Data reg #1 - never auto-increments (RW)
 * base + 0x6: Data reg #2 - side-effects as configured in WB config reg (RW)
 *
 * XXX note: two-cycle combine mode write cycles are currently broken. If a 32
 * bit core is used where 32 bit writes are required, this will have to be
 * revisited.  Otherwise, use 32 bit normal mode for writes.
 */
 
On the TS-4500 opencore design, the general purpose memory window appears at base address 0x18 in SBUS address space.  Currently, only two cores are connected to the memory window, the muxbus core and the user core.  To add a small custom feature to the TS-4500, it is recommended to put it in the user core.  To add a more complicated custom core, or an open core that already has a wishbone interface, it is recommended to incorporate it into memwindow address space.  The user core currently contains only the bus config register at offset 0.  The user core appears in memwindow address space at offset 0x20000.

Once the muxbus is configured using the bus config register, 16 bit external bus space is memwindow space 0x0 to 0xfffe.  8 bit external bus space is memwindow space 0x10000 to 0x1ffff.

The new sbus.c and sbus.h include winpeekxx and winpokexx functions for accessing memwindow space.  These serve as examples -- if bandwidth is an issue, then more sophisticated code will need to be written.

The pc104 utility is a sample utility to peek and poke 8 bit PC104 space on a TS-4500 mounted on a TS-81xx base board.