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Table of Contents

Introduction

The TS-7390 is a compact, flexible, affordable single board computer running Linux 2.6 out of the box.  The TS-TPC-7390 builds on the TS-7390 base board, adding a WVGA (800x480) TFT color touchscreen mounted in an aluminum frame attached to a bracket.

Hardware features include:

Software features include:

The TS-7390 is based on the Cirrus EP9302 Processor, which implements ethernet, USB, and two UARTs. For technical information on these functions please refer to the Cirrus user manual. The TS-7390 also utilizes a Lattice XP2 FPGA. Please refer to datasheets available from Lattice for more information.

Getting Started

The TS-9440B development console board (included in the development kit) is required for development with the TS-7390. Attach the TS-9440B to the JTAG header on the TS-7390, connect the 10 pin header COM adapter to the TS-9440B, and use that to connect to your development PC with a DB9 cable. Boot messages followed by a linux prompt should be displayed through the console.

The TS-7390 can be booted either from an SD card or from the on-board NAND flash.  If you did not purchase an SD card with your board, you can create a factory SD card using any 512MB or larger SD card. An SD card image is available here. When power is applied, the default boot behavior is fastboot, which provides a busybox prompt in under 2 seconds. After the busybox prompt is reached, the logo is displayed and X11 is started in the background.  It will typically take around 35 seconds for X11 and the icewm environment to load. If the fastboot shell is exited the X11 processes are terminated and the board continues on to perform a full Debian boot, after with X11 will be restarted.

The boot behavior is controlled by the linuxrc script, which by default is a symbolic link to linuxrc-fastboot. To automatically boot full Debian, link it instead to linuxrc-sdroot. Please note that changes made to files on the initial ramdisk are saved only in RAM. To save your changes permanently, type "save" at the fastboot prompt.

SD card features

The SD cards shipped with and for the TS-7390 contain a special four partition scheme. The first partition is a VFAT partition. On cards larger than 1GB, this partition contains Eclipse and other tools, documentation, and so forth. On cards smaller then 1GB this partition is empty. In either case you can use this partition to exchange files with a PC by plugging the SD card into a card reader attached to the PC.  The second partition contains a raw image of the kernel to be booted on the board, while the third partition contains an initial ramdisk (initrd) which the kernel uses as its root filesystem until the fastboot shell exits. The fourth partition contains the Debian Linux distribution, and contains the root filesystem that is used when the fastboot shell exits and the full boot commences.

Board specific features

LEDs

There are two LEDs on the TS-7390: one red and one green. Both LEDs comes on at power-up and and then turn off - the green light turns off quickly while the red LED fades off. The green and red LEDs are controlled through the CPU GPIO port E. They can be controlled using bits 0 and 1, respectively, of the port E register at address 0x8084_0020.

Random Number Generator

The TS-7390 has a built-in true random number generator (RNG). The number is generated from internal random entropy. The 32-bit value at address 0x600f_f0d0 contains the most recent random value generated. Only thirty-two bits of true random data are created every second, so if this register is read more quickly the values read are not guaranteed to be random: in fact, you will either read the same value as previously or else a pseudo-random intermediate value from the last value generated.

40 pin general header

The general header is a 40 pin (2x7, 0.1" spacing) header providing I2C, SPI, GPIO, latched outputs, buffered inputs, A/D inputs, an external reset line, and a console UART.

The general header is made up of two adjacent headers, labeled JTAG and DIO:

2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 18 20 22 24
1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 17 19 21 23
JTAG DIO

The pins on the 40 pin header serve a variety of functions. Refer to the table below to see which pins are available for each functionality.

Pin Number Name Function
JTAG 1 JTAG_DOUT Reserved
JTAG 2 JTAG_TMS Reserved
JTAG 3 GND Tied to ground
JTAG 4 JTAG_DIN Reserved
JTAG 5 HGPIO_3 DIO
JTAG 6 JTAG_CLK Reserved
JTAG 7 UART0_TXD UART0
JTAG 8 UART0_RXD UART0
JTAG 9 SPI_MISO SPI bus
JTAG 10 3.3V Tied to 3.3V
JTAG 11 HGPIO_5 DIO
JTAG 12 SPI_MOSI SPI bus
JTAG 13 FLASH_CS# Reserved
JTAG 14 SPI_CLK SPI bus
JTAG 15 EXT_RESET# External reset
JTAG 16 5V Tied to 5V
DIO 1 SPI_FRAME SPI bus
DIO 2 GND Tied to ground
DIO 3 RSVD Reserved
DIO 4 OUT_5 Latched output
DIO 5 IN_00 Buffered input
DIO 6 OUT_4 Latched output
DIO 7 IN_01 Buffered input
DIO 8 OUT_3 Latched output
DIO 9 IN_02 Buffered input
DIO 10 OUT_2 Latched output
DIO 11 IN_03 Buffered input
DIO 12 OUT_1 Latched output
DIO 13 IN_04 Buffered input
DIO 14 OUT_0 Latched output
DIO 15 IN_05 Buffered input
DIO 16 ADC4/BGPIO_7 ADC/DIO
DIO 17 IN_06 Buffered input
DIO 18 BGPIO_6 DIO
DIO 19 BGPIO_5 DIO
DIO 20 ADC2 ADC/Buffered input
DIO 21 I2C_SDA I2C
DIO 22 ADC1 ADC/Buffered input
DIO 23 I2C_SCL I2C
DIO 24 ADC0 ADC/Buffered input

Please note: Pins labeled "reserved" are used at the factory for production purposes and should not be used for applications.

Analog to Digital Conversion

Pins labeled ADC are available for analog to digital conversion using the Cirrus 5 channel A/D converter. Channels 0, 1, 2, and 4 are available for applications. Channel 3 is used internally.

Each of these pins, if not being used for A/D conversion, can instead be used as a buffered input, or in the case of pin DIO 16, a GPIO pin. For instructions on that please refer to the relevant section below.

DIO

Pins labeled "DIO" are connected directly to EP9302 GPIO pins. To use these pins, you must first set the data direction registers, and then read or write values from the data registers. When accessing these registers, it is important to do a read-modify-write, as other bits may be used internally. Pins labeled BGPIO are accessed through port B. The port B data direction register is located at address 0x80840014 and the port B data register is at 0x80840004. Pins labeled HGPIO are accessed through port H. The port H data direction register is located at address 0x80840044 and the port H data register is at 0x80840040.

Buffered Inputs

There are a total of 10 buffered digital input lines. Pins IN_0 through IN_6 are dedicated digital inputs, while pins IN_9 through IN_11 are in parallel with analog inputs and thus can only be used for digital input if analog inputs are not needed. Pins IN_0 through IN_3 have resistor pull-ups. The others will return random data if not driven high or low.

The 32 bit register at address 0x600f_f084 provides access to digital inputs. Pins IN_0 through IN_6 are accessed by bits 6 through 12. Pins IN_9 through IN_11 are accessed by bits 13 through 15.

Latched Outputs

Pins OUT_0 through OUT_5 are digital output lines. The 32 bit register at address 0x600f_f084 provides access to digital outputs through bits 0 through 5.

UART0

UART0_TXD and UART0_RXD (on the JTAG header) bring out the TTL level signals from the CPU. By default, this UART provides boot messages and the Linux console.  Under Linux this serial port is known as /dev/ttyAM0.

SPI Bus

The SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_FRAME pins bring out the SPI bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.

Real-Time Clock

The TS-7390 base board provides an optional Real-Time Clock module, consisting of an M48T86 series RTC and firmware support for the RTC on the base board.  The RTC is supported natively under the Linux 2.6 kernel shipping with the board.  Please consult the rtc-m48t86.c source file in the driver/rtc directory for more information on how the RTC is programmed.

I2C Bus

The I2C_SCL and I2C_SDA pins bring out the I2C bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.

External Reset

Driving the external reset pin low will reset the CPU. While the JFS file system on the SD card is extremely resilient and is normally not damaged by hard resets, rebooting the board using the reboot command is still recommended if the file system is mounted read/write.

Temperature Sensor (optional)

The TS-7390 has an optional on-board temperature sensor (part #:OP-TMPSENSE). The temperature sensor used is a TMP124; a copy of the datasheet can be found here, and sample code can be found here.

The temperature sensor is accessed via SPI pins on the DIO header documented in the previous section. The DATA pin on the TMP124 is connected to the SPI_MISO# signal, while the CLK pin is connected to the SPI_CLK pin. In addition there is a chip select signal which must be asserted in order to use the temperature sensor chip. This signal is accessed through bit 2 of the register at address 0x80840030. (CPU GPIO port F) Note that the polarity of this signal is active high (set this bit to select the temp sensor).

Expansion Bus

The 20-pin header located next to the battery-backed real-time clock (or next to the pads if the RTC option is not installed) provides an expansion bus.   Originally this was designed to talk directly to an SJ1000 (CAN) chip.  The software interface consists of two 8-bit registers: an address register mapped at 0x600FF410 and a data register at 0x600FF414.  Once an address is written, each read of the data register will cause a read bus cycle on the expansion bus and return the value read, and each write to the data register will cause a write bus cycle with the value written.

The pin diagram and the pin-out for the expansion bus is shown below:

2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
RTC side

Pin
 Name Function
1
 BUS_IOR#
2
 BUS_IOW#
3
 BUS_TXD
4
 BUS_D3
 data bit 3
5
 BUS_D1
 data bit 1
6
 BUS_D2
 data bit 2
7
 BUS_D4
 data bit 4
8
 BUS_D5
 data bit 5
9
 BUS_D6
 data bit 6
10
 BUS_D0
 data bit 0
11
 BUS_RXD
12
 BUS_D7
 data bit 7
13
 IRQ7
14
 3.3V
 3.3V power rail
15
 BUS_ALE
16
 NC
 no connection
17
 BUS_CS#
18
 CPU_RESET#
 Reset signal
19
 5V
 5V power rail
20
 GND
 ground rail
Signal names ending in "#" are active low.

The expansion bus is at offset 0x10 (address) and 0x14 (data) from the NAND registers, which are at offset 0x400 from base address of 0x600ff000.

 

Address Write Cycle

peekpoke 8 0x600ff410 0x55

 

          _                     

BUS_ALE__/ \___________________

          _____________________

BUS_D0 __/                    


 

Data Write Cycle

peekpoke 8 0x600ff414 0x55

           ____________________

BUS_D0  __/

        __   __________________

BUS_IOW#  \_/                   

        __   __________________

BUS_CS#   \_/                  

 


 

Data Read Cycle

peekpoke 8 0x600ff414


In this example, BUS_D0 is set up externally to the board.


            ___________________

BUS_D0   __/

         _____   ______________

BUS_IOR#      \_/

         _____   ______________

BUS_CS        \_/

 

Note: In the above examples, for simplicity only BUS_D0 is shown.   For clarity in showing transition points, it is assumed that the pre-existing state of this bit will be opposite of the new value; this will not always be the case.

UARTs

In addition to the serial console there are 7 additional serial ports.  One is implemented in the EP9302 and the remaining ports are TS-UARTs.  Under Linux the second EP9302 serial port is known as /dev/ttyAM1, and this port goes to the COM1 header.

The remaining TS-UARTs have Linux device names of /dev/tttsX, where X is the TS-UART number, starting with 0.  The table below summarizes the TS-UART ports:

#
 RS-
 base adrs
 header
 Tx / X+
 Rx / X-
 TxEn
 RTS
 CTS
0
 232
 0x600FF0A0
 COM2
 3 (TXD)
 2 (RXD)
 N/A
 no
 no
1
 232
 0x600FF0A4 COM1
 7 (RTS)
 8 (CTS)
 N/A
 no
 no
2
 232
 0x600FF0A8 COM1
 4 (DTR)
 1 (DCD)
 N/A
 no
 no
3
 485
 0x600FF0AC
 COM2
 1 (DCD) 6 (DSR)
 auto
 N/A
 N/A
4
 485
 0x600FF0B0
 COM2
 4 (DTR)
 9 (RI)
 auto
 N/A
 N/A
5
 TTL
 0x600FF0B4
 expansion bus
 3 (BUS_TXD)
 11 (BUS_RXD)
 N/A
 no
 no

TS-UART registers are 16-bits wide.


Audio Speaker

The TS-TPC-7390 provides audio capabilities via a mono speaker, which a codec that supports up to a12kHz sample rate.  The playsound utility is provide, both compiled into busybox and also as a standalone utility, which can play sounds to this speaker. It can play most types of sound file if the "sox" command is in the path, otherwise it just plays WAV files.    The playsound utility will down-sample automatically as needed.  Sound is played by writing samples to a 4096(x16 bit) sample buffer in the FPGA. The source code for playsound is available to illustrate how this is done.


Touch Screen LCD

The TS-TPC-7390 LCD panel is a WVGA (800x480) display with built-in touchscreen.  The touchscreen provides 12-bit A/D samples for both X and Y axes, for a nominal resolution of 4096x4096.  Calibration of the touch screen is stored in FPGA tag memory along with other data.  The Linux touchscreen driver (drivers/input/ts_lcd.ko) provides raw data from the touch screen to the generic linux evdev driver which provides a standard interface in /dev/event0.

Sample code (tstest.c) is available which demonstrates how to use the LCD, either through the Linux device drivers, or via direct hardware access.

Backlight control is provided.  The backlight can be enabled and dimmed.  This is controlled through the 16-bit register at address 0x600FF086.  Setting bit 14 turns on the backlight, while clearing it turns the backlight off.  Setting bit 13 dims the backlight while clearing it undims it.

Video Core

The LCD panel video core is based on the TS-7KV core.  The register definitions for the FPGA registers and video RAM for the TS-7KV are used in the TS-7390.  The base addresses are:

FPGA registers 0x600FF030
Video RAM 0x60100000


Touchscreen Registers

The current location the touchscreen is being pressed can be read from the X and Y A/D registers at address 0x600FF020 and 0x600FF022, respectively.  These registers are 16-bit, formatted as follows:

bit(s)
 description
15:4
 inverted A/D value
3:1
 unused
0
 reading value (0 if no touch detected)


It is recommended to debouncing the transition from invalid to value.   This can be done by ignoring the first 40ms of readings after the valid bit transitions high, and resetting this timer whenever the valid bit transitions low.

The readings from the touch screen should be processed and calibrated using the following formulas:

x = ( (~X) >> 0xFFF - calib_x0 ) * 4096 / calib_dx;
y = ( (~Y) >> 0xFFF - calib_y0 ) * 4096 / calib_dy;


Tag Memory


There are 136 bytes of "tag memory" or FPGA internal flash used to store various configuration values.  The structure of this storage area follows:

offsets
 description
0-2
 last three bytes of board MAC address
3
 sysinfo
bit 7 = industrial grade
bits 6:0 = reserved
4-7
 born-on date (represented in seconds since 00:00:00 UTC, January 1, 1970
8-27
 ADC calibration values
5 A/Ds,2 signed 16-bit values per A/D (12-bits of resolution)
first value is the 0V value, second is the 3.3V value
28-35
 touch screen calibration values
16-bit values "calib_x0", "calib_dx", "calib_y0", "calib_dy"
36-75
 available for user

Calibration values are stored in little endian format. Sample code (tagmem.c) is available which demonstrates how to read and write to the tag memory.