The TS-7390 is a compact, flexible, affordable single board computer
running Linux 2.6 out of the box. The TS-TPC-7390 builds on the
TS-7390 base board, adding a WVGA (800x480) TFT color touchscreen
mounted in an aluminum frame attached to a bracket.
The TS-7390 is based on the Cirrus EP9302 Processor, which implements ethernet, USB, and two UARTs. For technical information on these functions please refer to the Cirrus user manual. The TS-7390 also utilizes a Lattice XP2 FPGA. Please refer to datasheets available from Lattice for more information.
The TS-9440B development console board (included in the development kit) is required for development with the TS-7390. Attach the TS-9440B to the JTAG header on the TS-7390, connect the 10 pin header COM adapter to the TS-9440B, and use that to connect to your development PC with a DB9 cable. Boot messages followed by a linux prompt should be displayed through the console.
The TS-7390 can be booted either from an SD card or from the
on-board NAND flash. If you did not purchase an SD card with your
board, you can create a factory SD card using any 512MB or larger SD
card. An SD card image is available here.
When power is applied, the default boot behavior is fastboot, which
provides a busybox prompt in under 2 seconds. After the busybox prompt
is reached, the logo is displayed and X11 is started in the
background. It will typically take around 35 seconds for X11 and
the icewm environment to load. If the fastboot shell is exited the X11
processes are terminated and the board continues on to perform a full
Debian boot, after with X11 will be restarted.
The boot behavior is controlled by the linuxrc script, which by default is a symbolic link to linuxrc-fastboot. To automatically boot full Debian, link it instead to linuxrc-sdroot. Please note that changes made to files on the initial ramdisk are saved only in RAM. To save your changes permanently, type "save" at the fastboot prompt.
The SD cards shipped with and for the TS-7390 contain a special four partition scheme. The first partition is a VFAT partition. On cards larger than 1GB, this partition contains Eclipse and other tools, documentation, and so forth. On cards smaller then 1GB this partition is empty. In either case you can use this partition to exchange files with a PC by plugging the SD card into a card reader attached to the PC. The second partition contains a raw image of the kernel to be booted on the board, while the third partition contains an initial ramdisk (initrd) which the kernel uses as its root filesystem until the fastboot shell exits. The fourth partition contains the Debian Linux distribution, and contains the root filesystem that is used when the fastboot shell exits and the full boot commences.
There are two LEDs on the TS-7390: one red and one green. Both LEDs
comes on at power-up and and then turn off - the green light turns off
quickly while the red LED fades off. The green and red LEDs are
controlled through the CPU GPIO port E. They can be controlled using
bits 0 and 1, respectively, of the port E register at address
The TS-7390 has a built-in true random number generator (RNG). The number is generated from internal random entropy. The 32-bit value at address 0x600f_f0d0 contains the most recent random value generated. Only thirty-two bits of true random data are created every second, so if this register is read more quickly the values read are not guaranteed to be random: in fact, you will either read the same value as previously or else a pseudo-random intermediate value from the last value generated.
The general header is a 40 pin (2x7, 0.1" spacing) header providing I2C, SPI, GPIO, latched outputs, buffered inputs, A/D inputs, an external reset line, and a console UART.
The general header is made up of two adjacent headers, labeled JTAG
The pins on the 40 pin header serve a variety of functions. Refer to the table below to see which pins are available for each functionality.
|JTAG 3||GND||Tied to ground|
|JTAG 9||SPI_MISO||SPI bus|
|JTAG 10||3.3V||Tied to 3.3V|
|JTAG 12||SPI_MOSI||SPI bus|
|JTAG 14||SPI_CLK||SPI bus|
|JTAG 15||EXT_RESET#||External reset|
|JTAG 16||5V||Tied to 5V|
|DIO 1||SPI_FRAME||SPI bus|
|DIO 2||GND||Tied to ground|
|DIO 4||OUT_5||Latched output|
|DIO 5||IN_00||Buffered input|
|DIO 6||OUT_4||Latched output|
|DIO 7||IN_01||Buffered input|
|DIO 8||OUT_3||Latched output|
|DIO 9||IN_02||Buffered input|
|DIO 10||OUT_2||Latched output|
|DIO 11||IN_03||Buffered input|
|DIO 12||OUT_1||Latched output|
|DIO 13||IN_04||Buffered input|
|DIO 14||OUT_0||Latched output|
|DIO 15||IN_05||Buffered input|
|DIO 17||IN_06||Buffered input|
|DIO 20||ADC2||ADC/Buffered input|
|DIO 22||ADC1||ADC/Buffered input|
|DIO 24||ADC0||ADC/Buffered input|
Please note: Pins labeled "reserved" are used at the factory for production purposes and should not be used for applications.
Pins labeled ADC are available for analog to digital conversion using the Cirrus 5 channel A/D converter. Channels 0, 1, 2, and 4 are available for applications. Channel 3 is used internally.
Each of these pins, if not being used for A/D conversion, can instead be used as a buffered input, or in the case of pin DIO 16, a GPIO pin. For instructions on that please refer to the relevant section below.
Pins labeled "DIO" are connected directly to EP9302 GPIO pins. To use these pins, you must first set the data direction registers, and then read or write values from the data registers. When accessing these registers, it is important to do a read-modify-write, as other bits may be used internally. Pins labeled BGPIO are accessed through port B. The port B data direction register is located at address 0x80840014 and the port B data register is at 0x80840004. Pins labeled HGPIO are accessed through port H. The port H data direction register is located at address 0x80840044 and the port H data register is at 0x80840040.
There are a total of 10 buffered digital input lines. Pins IN_0 through IN_6 are dedicated digital inputs, while pins IN_9 through IN_11 are in parallel with analog inputs and thus can only be used for digital input if analog inputs are not needed. Pins IN_0 through IN_3 have resistor pull-ups. The others will return random data if not driven high or low.
The 32 bit register at address 0x600f_f084 provides access to digital inputs. Pins IN_0 through IN_6 are accessed by bits 6 through 12. Pins IN_9 through IN_11 are accessed by bits 13 through 15.
Pins OUT_0 through OUT_5 are digital output lines. The 32 bit register at address 0x600f_f084 provides access to digital outputs through bits 0 through 5.
UART0_TXD and UART0_RXD (on the JTAG header) bring out the TTL level
signals from the
CPU. By default, this UART provides boot messages and the Linux
console. Under Linux this serial port is known as /dev/ttyAM0.
The SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_FRAME pins bring out the
SPI bus from the EP9302 CPU. Please refer to the EP9302 user's guide
for more information.
The TS-7390 base board provides an optional Real-Time Clock module,
consisting of an M48T86 series RTC and firmware support for the RTC on
the base board. The RTC is supported natively under the Linux 2.6
kernel shipping with the board. Please consult the rtc-m48t86.c
source file in the driver/rtc directory for more information on how the
RTC is programmed.
The I2C_SCL and I2C_SDA pins bring out the I2C bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.
Driving the external reset pin low will reset the CPU. While the JFS file system on the SD card is extremely resilient and is normally not damaged by hard resets, rebooting the board using the reboot command is still recommended if the file system is mounted read/write.
The TS-7390 has an optional on-board temperature sensor (part #:OP-TMPSENSE). The temperature sensor used is a TMP124; a copy of the datasheet can be found here, and sample code can be found here.
The temperature sensor is accessed via SPI pins on the DIO header documented in the previous section. The DATA pin on the TMP124 is connected to the SPI_MISO# signal, while the CLK pin is connected to the SPI_CLK pin. In addition there is a chip select signal which must be asserted in order to use the temperature sensor chip. This signal is accessed through bit 2 of the register at address 0x80840030. (CPU GPIO port F) Note that the polarity of this signal is active high (set this bit to select the temp sensor).
||data bit 3
||data bit 1|
||data bit 2|
||data bit 4|
||data bit 5|
||data bit 6|
||data bit 0|
||data bit 7|
||3.3V power rail
||5V power rail
expansion bus is at
offset 0x10 (address) and 0x14 (data) from the NAND registers, which
at offset 0x400 from base address of 0x600ff000.
Address Write Cycle
peekpoke 8 0x600ff410 0x55
Data Write Cycle
peekpoke 8 0x600ff414 0x55
Data Read Cycle
peekpoke 8 0x600ff414
In this example, BUS_D0 is set up externally to the board.
Note: In the above examples, for simplicity only BUS_D0 is shown. For clarity in showing transition points, it is assumed that the pre-existing state of this bit will be opposite of the new value; this will not always be the case.
In addition to the serial console there are 7 additional serial
ports. One is implemented in the EP9302 and the remaining ports
are TS-UARTs. Under Linux the second EP9302 serial port is known
as /dev/ttyAM1, and this port goes to the COM1 header.
The remaining TS-UARTs have Linux device names of /dev/tttsX, where X is the TS-UART number, starting
with 0. The table below summarizes the TS-UART ports:
||Tx / X+
||Rx / X-
||1 (DCD)||6 (DSR)
TS-UART registers are 16-bits wide.
||inverted A/D value
||reading value (0 if no touch
||last three bytes of board MAC
bit 7 = industrial grade
bits 6:0 = reserved
||born-on date (represented in seconds since 00:00:00 UTC, January 1, 1970|
||ADC calibration values
5 A/Ds,2 signed 16-bit values per A/D (12-bits of resolution)
first value is the 0V value, second is the 3.3V value
||touch screen calibration values
16-bit values "calib_x0", "calib_dx", "calib_y0", "calib_dy"
||available for user